Authors: Florin Babarada,Adrian Rusu, Tudor Niculiu, Cristian Ravariu, Dragos Vizireanu, Carmen Moldovan, Elena Manea,Camelia Dunare, Madalina Mlak
The challenges of the integrated circuits and nanotechnology need very accurate models for active devices. From this point of view the design of linear analog circuits lacks models for state-of-the-art MOS transistors to accurately describe distortion effects. This is produced by the inaccurate modelling of the second order effects induced by high vertical gate field such as mobility degradation and short channel series resistance and second order effects induced by parallel drain field like velocity saturation in the ohmic region, channel length modulation in the saturation region, static feedback and weak avalanche. After a rigorous description of transistor transconductance and channel conductance in ohmic and saturation region we included these effects in the MOS transistor model, using a compact expression of drain current for computation reasons. The simulations using the new drain current expression were in good agreement with experimental data, proves scalability and large voltage range functionality.